Serial-to-parallel converters are used across various computing devices and for various applications. For instance in a peripheral component interconnect express (“PCIe”) serial interface, double data rate data is inputted to a receiver of the PCIe. The receiver converts the double data rate data to a parallel word of different widths.
Typically, when an input word is converted from serial data to parallel data, a serial input signal for the input word is stored in a shift register through successive shifting of the input signal. When the input word of the serial input signal has been stored in the shift register, the whole stored input word is transferred at one time to a buffer register having bit positions corresponding to those of the shift register. The contents of the buffer register, representing the bits of the input word, are outputted in parallel. Thereby, the serial input word is outputted in parallel. The serial-to-parallel converter implemented in this manner consumes large amounts of power in comparison to other serial-to-parallel converter techniques.
Another typical serial-to-parallel converter (“SPC”) uses a tree-like circuit having several stages for storing serial bits in multiple increments of 2 bits. The first stage can store 2 bits from the serial data word. The first stage outputs the 2 bits to a second stage that stores 4 bits from the first stage. The next stage can store 8 bits from the second stage. This process continues in the subsequent stages until 2N bits are stored for output in parallel. Unfortunately, such serial-to-parallel converter has the problem that the circuit size becomes greater than a typical shift-register-type converter when the number of bits to be outputted in parallel increases. Also, the number of stages can dramatically increase as the number of bits to be outputted in parallel increases, thereby, increasing the latency which is a function on the number of stages of the SPC. Furthermore, the SPC cannot be adjusted for input words that are not exactly 2N bits in word size.
Therefore, there exists a need for a novel SPC that has low latency and a predefined number of stages for converting a serial data word to a parallel word.